This invention relates to semi-conductor memories and more particularily to improvements therein.
In the layout of a semi-conductor memory, usually the memory cells are laid out in an array of columns and rows. There are usually two sense lines for each cell and a pair of sense lines is connected to a column of cells. As a result, in the memory array, the pairs of sense lines are adjacent and parallel to one another. In the operation of the memory, usually, one of the sense lines will remain at its initial voltage, usually a high voltage, and the other sense line of each pair will change states, usually going from a high to a low voltage.
As a result of the foregoing, coupling occurs between these sense lines which has the effect of causing transients to appear, as the result of which, the operation of any sensing circuits used to obtain a differential signal from the sense line has to slow down, in order to avoid an erroneous reading. This of course slows the cycle time for a memory and thereby slows the entire equipment which uses the memory.